Digital Design IMAMU CS 106
It is the basis for building any logical circuit and then to a digital system and it is in most devices and through it you can control the device you want.
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NEW SLIDE
- Chapter 1 Numbe System 43:15
- Chapter1 Signed number 48:42
- Chapter 2 boolean function 21:33
- Chapter 2 Conancial form 01:04:46
- Chapter 2 HW 06:16
- Chapter 3 two ,three variable KMAP 33:59
- Chapter 3 four variable 01:01:54
- Chapter4 Binary Adder 42:13
- Chapter 4 decoder, multiplexer 44:53
- chapter 4 design procedure 09:34
- Chapter 5 latch 21:10
- Chapter 5 analysis D f.f 23:40
- Chapter 5 JK flipflop 17:41
- Chapter5 Tflipflop 09:03
- Chapter 5 design detector 21:09
- Chapter 5 Register 24:29
- Excitation table 08:32
- Mealy ,Moore Model 07:10
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New Sheet
- Sheet 1part1 25:30
- Sheet 1 part2 36:18
- New sheet1 34:10
- SHEET 2 UPDATED 45:38
- SHEET2 50:22
- Sheet2 part 2 21:15
- NEW SHEET 3 01:05:23
- sheet 4 part1 37:23
- Sheet 4 PART 2 36:44
- Sheet4 part 4 16:33
- Sheet 4 part3 31:11
- Sheet 4 OLD 27:32
- Sheet 3 01:06:20
- Sheet ch5 part 1 33:22
- Sheet ch5 part 2 34:26
- SHEET 5 PART 3* 27:08
- Sheet ch5 part 3 10:36
- Example drawing NOR ,NAND 09:34
- DRAWING HW SHEET5 04:26
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MID1
- important example for Quiz 04:38
- Exercise chapter 1 08:44
- EXAM QUIZ CH2,3,4 10:32
- MID 2023 CH1,2,3 31:35
- Revision Chapter1 book 22:55
- MID_EXAM1 22:19
- EXAM ch1,2 20:06
- IMPORTANT EXAM 07:35
- QUESTION Ch2 06:14
- Revision chapter2 33:13
- Example chapter2 02:37
- REVISION1_chapter3 27:18
- Revision chapter3 53:13
- Revision chapter1 38:57
- التحويلات العدديه بدون حاسبه 19:56
- ريفيشن شابتر 2 25:57
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Old SHEET
- SHEET1 24:03
- sheet 1_signed number 18:03
- Sheet 3 chapter1 33:59
- Sheet1 , Sheet2 part 1 Chapter 1 17:21
- Sheet2 chapter1 part2 12:23
- chapter2 Sheet4 26:56
- sheet chapter2 extra 42:47
- sheet3 on ch2,3 part 1 23:51
- sheet 3 on ch2,3 part2 16:55
- sheet3 on ch2,3 part 3 23:10
- Sheet ch4 11:04
- Chapter 3 Sheet 5 41:07
- Chapter3 sheet 6 15:44
- sheet chapter3 extra 48:21
- Sheet 8 chapter 4 part 1 56:37
- Sheet 8 part 2 chapter 4 18:35
- sheet CH4 PART1 21:51
- sHEET CH4 PART2 21:43
- extra sheet chapter 4 30:03
- sheet chapter 4 20:54
- Sheet ch5 Timing Diagram 20:15
- sheet chapter 5 # 35:54
- SHEET5 EXAMLE D 01:45
- sheet chapter 5 30:10
- Sheet chapter 5 59:30
- سؤال 6 بشيت 5 12:21
- Sheet 9_chapter5_part1 39:19
- Sheet9-chapter 5-part2 39:29
- SHEET9-chapter 5-Question 9 14:11
- Sheet 5 part1 31:14
- sheet5 part2 28:13
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FINAL_LAB
- LAB_FLIPFLOP 09:32
- طريقه رسم الديكودر والسيركت 13:24
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Project 2024
- project 2024 task 1,task2 28:47
- project 2024 task3 33:15
- Lab 1 combinational circuit 19:33
- BCD TO SEVEN SEGMENT 26:28
- Drawing b,e ,f,d using Nor,Nand 05:36
- project 1 20:18
- project 2 12:51
- PROJECT TASK1,TASK2 24:24
- project Q2 BCD DECODING 39:01
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ch5
- Chapter 5 SequntiaStorage element 21:49
- SR Latch 27:42
- Flip Flop 17:31
- D flip flop 23:40
- J K Flip Flop 17:41
- T Flip Flop 09:03
- Design Procedure 21:09
- Register 24:29
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MID2
- MID2 NEW* 19:35
- Mid exam ch5,4 important 24:07
- QUIZ CH4,3 38:08
- MID2 NEW 2022 SUMMER 09:28
- MID_EXAM2 30:43
- MID CH4,3 25:03
- EXAM CH3,4 08:36
- Revision decoder,Multiplexer 23:45
- Revision design combinational circuit 22:30
- Example binary adder subtructor 04:40
- Revision ch4 39:41
- REVISION4,5 31:35
- Multiple-choice ch4 30:07
- Important exam ch1,2,3,4 18:51
- تمارين شابتر 4 الجزء الثاني 47:15
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PROJECT old
- PROJECT 10:43
- project truth table ,map 17:51
- Logisim_drawing 05:23
- PROJECT NEW 11:56
- DRAWING VOTE SYSTEM 07:46
- PROJECT2 06:24
- project2 drawing 03:10
- Project circuit logisim part1 17:31
- Design Circuit logisim part 2 01:27
- NEW PROJECT 18:08
- Project DownCounter 11:44
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Logisim LAB
- LAB CIRCUIT 24:35
- LAB Sequential circuit 24:35
- LAB 2 EXAM 30:37
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Summer 2023
- Ch1 Introduction 24:40
- Ch1 Conversion Number 01:03:01
- Ch1 Addition Subtruction 15:53
- Ch1 Complement 31:17
- Ch1 Subtruction Unsigned Number 19:47
- Ch1 Signed,BCD 01:07:03
- Chapter 2 boolean function 41:33
- Chapter 2 implement function 51:26
- CHAPTER 3 KMAP PART 1 36:44
- CHAPTER 3 KMAP PART 2 47:02
- CHAPTER 3 PART 3 NAND NOR 22:03
- CHAPTER 3 EXTRA PRIME IMPLICANT 01:21:13
- Chapter 3 prime -don't care 47:42
- CHAPTER4 PART 1 26:07
- CHAPTER 4 PART 2 42:03
- CHAPTER 5 PART 1 32:56
- CHAPTER 5 PART 2 14:49
- CHAPTER 5 PART 3 43:29
- Ch5 register 40:23
- Mealy ,Moore model 07:10
- Chapter 5 problem with latches 46:58
- Signed number old 39:23
- Subtraction signed number old 42:23
- BCD old 17:10
- HOME WORK 10:06
- Chapter1 Introduction ,Number system old 48:50
- convert D to T FLIP FLOP 06:16
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FINAL REVISION
- Final 2023 41:24
- Final Exam New 17:34
- Important exam chapter5 07:32
- true,false 05:00
- Final_Exam 17:17
- Final 2 30:43
- EXAM CHAPTER 5,6 BLACKBOARD 15:01
- EXAM CH6,5 EXTRA BLACKBOARD 11:53
- EXAM 2 CH5,6 09:18
- example shifT REGISTER ,DOWNCOUNTER 10:36
- MID2 2022 08:30
- final revision 1 27:08
- Revision_chapter 6 26:54
- Revision chapter 5 59:17
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NEW SLIDE
- It is the basis for building any logical circuit and then to a digital system and it is in most devices and through it you can control the device you want.
-
My name is Sara I 'm electronic and communication engineer.
Sara Qualifications: Masters in Networks and Communications.
Sara Experiences:
1- professor at the National Institute of Communications for training computer network courses like CCNA ,CCNP , computer programs.
2- Sara experiences 10 years for teaching Princess Noura University subjects as :
* communications and network fundamentals It222
*computer network fundamentals it221
* Digital Logical design cs105
* Information Security it311
*advanced computer network net431
*Satellite Communication it425
*Wireless Network it331
*Network security net412d
* Network King saud university
*Digital logic design IMAMU University
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Lectures
173 Videos
Duration
75:15:08
Material
36 Files
Assignments
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Labs
Yes, Completely
Project
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Certificate
Not Applicable
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