Digital logic Circuit Design ECE 260
This course deals with the digital logic circuit design. It starts with a presentation of the systems numbers and code, the logic gates, the Boolean algebra, and Karnaugh maps. It covers the design a
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Chapter 1 #
- Digital Systems 12:43
- Number Systems 21:33
- Convert Decimal to Binary 12:12
- Binary arithmetic Addition 10:30
- Binary arithmetic Multiply ,Division 16:45
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Chapter 2#
- Octel ,Hexadecimal Number 19:24
- SIgned Magnitude Representation 21:28
- Radix complement 18:44
- Subtraction Signed Number 15:14
- Binary Code 31:03
- Binary Logic AND,OR,NOT 11:42
- Signed number 18:52
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Revision
- Important Question ch2 07:09
- Chapter 1 HW 16:12
- Revision CH 1 , 2 35:04
- Revision Chapter 3 16:09
- Revision Chapter 3 part 2 38:46
- REVISION CH4 21:28
- Revision CH5 15:46
- Revision Chapter 6 Design Procedure 22:30
- Rev CH 6 Example binary adder subtractor 04:40
- Revision Chapter7 19:54
- Revision CH 8,9 30:28
- Extra Revision ch8,9 11:52
- Revision chapter 10 29:52
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Tutorial
- Tutorial 1 part 1 25:07
- Tutorial 1 part 2 09:42
- Tutorial 2 37:32
- Tutorial 2 Q9 02:25
- Tutorial 3 part1 22:50
- Tutorial 3 part 2 21:20
- Tutorial 3 Q6 13:09
- Tutorial 4 Q1 03:26
- Tutorial 4 21:28
- Tutorial 5 31:30
- Tutorial 6 45:33
- Tutorial 6 sum ,Carry Equation 06:32
- Tutorial 7 23:49
- Tutorial 8 part 1 34:58
- Tutorial 8 part 2 12:52
- Tutorial 9 33:28
- Tutorial 10 15:03
- Tutorial 11 12:30
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Previous Exam
- MID1 EXAM 15:23
- Mid 2023 26:23
- QUIZ1 2024 CH1,2 13:20
- Quiz CH 1,2 11:45
- EXAM CH4 08:59
- Final Exam1 32:54
- MID EXAM Example decoder ,mux 12:03
- final revision * 13:21
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Chapter 3#
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Chapter 4#
- Kmap Two Variable 19:11
- Three variable Map 29:30
- Four variable Map 16:20
- Prime Implicant , Essential prime 29:00
- Sum Of Product ,Product Of Sum 14:09
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Chapter 5#
- Don't care 17:07
- NAND Implementation 20:47
- NOR Implementation 25:30
- Exclusive -OR 15:17
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Chapter 6#
- Analysis Procedure 21:49
- Design Procedure 17:06
- Half Adder , Full Adder 17:26
- Binary Adder 23:40
- Binary subtractor , Overflow 20:31
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Chapter 7#
- Decimal Adder 22:45
- Magnitude Comparetor 16:23
- Decoder 26:12
- Encoder 19:06
- Multiplexer ,Demultiplexer 28:13
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Chapter 8#
- Sequential Circuit 10:44
- Latches & Flip flop 14:34
- Edge triggered D Flip flop 22:40
- Convert D Flip flop to T flip flop 06:16
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Chapter 9#
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Chapter 10#
- Register 12:18
- Shift Register 13:19
- Universal Shift Register 11:24
- Counter 15:33
- Design Counter 13:51
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Chapter 11 #
- Random Access Memory 21:46
- Memory Decoding 14:23
- Read Only Memory 18:00
- Programable Logic Array 18:18
- Sequential Programable Device 12:02
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LAB 2024
- LAB3 (LOGIC CONVERTER) 04:02
- Lab 3 updated 15:15
- Lab4 updated 21:53
- LAB 5 updated 19:00
- lab 5 updated drawing 20:56
- LAB6 UPDATED* 24:54
- LAB 8 MUX-DEMUX 14:16
- LAB 7 part 1 updated 20:19
- LAB7 PA2 updated 10:08
- LAB 7 PART 1 17:17
- lab 7 multisim Q1,2 08:00
- LAB 8 05:10
- LAB 9 24:39
- LAB 10 17:53
- LAB 11 16:49
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LAB 2025
- LAB 1 assignment 07:29
- LAB2 11:41
- Lab 3 08:12
- lab 3 drawing multisim 05:03
- LAB 3 HW 02:49
- LAB 4 05:46
- Final Lab Part 1 09:01
- Final Lab Part 2 14:48
- LAB 5 10:28
- LAB 6 13:25
- LAB 7 24:27
- LAB 7 EXTRA Q1 11:42
- LAB7 EXTRA Q2 13:56
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LAB #
- Lab 1 35:32
- Lab 2 updated 06:35
- LAB 2 Assignment 07:29
- Lab 3 05:46
- lab 4 drawing 03:51
- LAB 8 Q1 07:52
- LAB8 Q2,3 16:37
- LAB 8 Q 3 DRAWING 07:23
- LAB 3 20:21
- LAB 5 32:44
- lab 5 multisim 02:43
- LAB 7 Q3,4 08:19
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Chapter 1 #
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This course deals with the digital logic circuit design. It starts with a presentation of the systems numbers and code, the logic gates, the Boolean algebra, and Karnaugh maps.
It covers the design and analysis of combinational logic systems using logic gates, decoders, encoders, multiplexers, demultiplexers, adders, and subtractors. It also includes the design of sequential logic using the latches, flip-flops. Some sequential circuits components are also presented in this course, such as registers, shift registers, and counters.
Memory (RAM) and programmable logic devices are introduced and some combinational and sequential
programmable devices are presented such as Field-programmable gate arrays (FPGAs).
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Lectures
134 Videos
Duration
38:55:07
Material
55 Files
Assignments
Yes, Completely
Labs
Yes, Completely
Project
Yes, Completely
Certificate
Not Applicable
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